The present exemplary embodiments relate to mitigating particle contamination on the backside of a semiconductor wafer, and more particularly, relate to mitigating particle contamination by providing a patterned surface on the backside of the semiconductor wafer to capture the contaminating particulate matter within the patterned features.
Particulate matter may be generated from wafer handling devices (such as pics, pins and pads) as the semiconductor wafers travel through a multitude of tools in the line. Some particulate matter, and especially scratches and dents, are inevitable, regardless of any sort of preemptive cleaning or wiping methods.
The semiconductor wafers are typically handled with a so-called wafer chuck, one example of a wafer chuck being an electrostatic wafer chuck, which secures the semiconductor wafer during processing. However, conventional electrostatic chucks maintain a high percent point of contact with the backside of the semiconductor wafer. This large area of contact is highly susceptible to semiconductor wafer backside particulate manner and scratches, which can create wafer topography during lithography exposure and lead to “hot spots”. A hot spot in the present context is a lithography term for a localized pattern distortion (i.e., defocus) of which one cause is wafer topography.